Intel brought three chips to Hot Chips 2026: a 256-core Xeon, an inference GPU that trades HBM for LPDDR5X, and a shipping edge chip. The specifications, the disagreements between reports, and what is still unconfirmed.
Intel Diamond Rapids, the company’s next Xeon, is built around 256 cores, 1.28 GB of last-level cache and 16 memory channels. It was one of three chips Intel put in front of engineers at Hot Chips 2026 in late August. The other two were Crescent Island, an air-cooled inference accelerator that uses LPDDR5X where rivals use HBM, and Wildcat Lake, a small client and edge chip that is already shipping. Intel ties all three to agentic AI: software that plans, calls tools and loops back, which stresses a processor differently than a single chatbot reply does.
Most of what follows comes from two write-ups of Intel’s presentations, one from StorageReview and one from TechRadar. They agree on the headline specifications and split on a few details. Those splits are flagged below instead of smoothed over. Intel has not given pricing or a power figure for Diamond Rapids in either report, so none appear here.
- Diamond Rapids: up to 256 cores, 1.28 GB last-level cache, 16 memory channels up to 12,800 MT/s, 128 PCIe Gen6 lanes, CXL 3.0, built on Intel 18A-P.
- Crescent Island: Xe3P inference GPU with 32 Xe cores and 256 XMX engines, a 350 W air-cooled PCIe card, LPDDR5X instead of HBM, memory bandwidth undisclosed.
- Wildcat Lake: Core Series 3 chip with 2 performance and 4 efficiency cores, Xe3 graphics and an NPU of up to 17 TOPS, shipping now in mini PCs and laptops.
- Open questions: the reports disagree on Crescent Island’s memory ceiling (480 GB versus 160 GB on Intel-branded cards) and on Wildcat Lake’s packaging details.
Why Intel framed the talks around agentic AI
A single chat request is mostly one long burst of matrix math. An agent behaves differently. It reads a task, drafts a plan, calls a search tool, parses what comes back, queries a database, checks its own output and tries again. Each of those steps is a small piece of ordinary software wrapped around a model call, and the model call itself may be short.
Intel’s argument, as both outlets relay it, is that this mix calls for general-purpose compute, dedicated acceleration and fast links between them, rather than one oversized accelerator doing everything. Chief technology officer Pushkar Ranade said agentic AI changes how the company designs computing “from the transistor upward,” per TechRadar. According to StorageReview, Intel says all three platforms rely on Foveros Direct 3D stacking and UCIe, the open die-to-die interconnect standard, to meet power, bandwidth and density targets.
Read that as positioning, not proof. No benchmark in either report shows an agentic workload running faster on these parts. What the presentations do supply is hardware detail, and that is where the useful material sits.
Diamond Rapids: 256 cores as an orchestration engine
StorageReview describes Diamond Rapids as the workload-orchestration tier: the processor that schedules agents, runs the tool calls and feeds accelerators. The specifications it reports are up to 256 cores, 1.28 GB of last-level cache, Foveros Direct 3D stacking and UCIe-S links joining modular compute tiles, and Intel 18A-P as the process. TechRadar adds, citing ServeTheHome, that the largest configuration reportedly uses 16-core chiplets. If that holds, 256 cores means 16 of them.
Memory and I/O carry the rest of the story. The chip has 16 memory channels at up to 12,800 MT/s. Assuming standard 64-bit channels (an assumption, since neither report states the width), peak theoretical bandwidth works out to roughly 1.6 TB/s: 12,800 MT/s times 8 bytes is 102.4 GB/s per channel, times 16. For input and output there are 128 lanes of PCIe Gen6 plus CXL 3.0. At 64 GT/s per lane, that is about 1 TB/s in each direction before encoding and protocol overhead, again by simple arithmetic. For what Gen6 means on the storage side, see the earlier post on PCIe 6.0 SSDs in data centers.
On the instruction side, StorageReview lists Intel APX, which extends the x86 register file, and updated AMX matrix instructions. TechRadar compares the chip with AMD’s 256-core EPYC 9996, which it says is built on TSMC 2nm with simultaneous multithreading, and notes Diamond Rapids has about half the threads. TechRadar also says the part arrives in 2027. StorageReview’s summary gives no launch timing, socket or power rating, so treat the date as reported, not confirmed by Intel in these sources.
Crescent Island: the inference card that skipped HBM
Crescent Island is built on the Xe3P architecture with 32 Xe cores and 256 XMX matrix engines, which is eight engines per core. TechRadar adds 32 MB of unified L2 cache. It is a 350 W, air-cooled card in a standard PCIe form factor, so it fits ordinary servers without liquid cooling. The choice that stands out is memory: LPDDR5X, not HBM.
That is a trade, and bandwidth is what Intel has not disclosed. Token generation in a large language model is usually limited by how fast the weights can be read from memory, so a rough ceiling on tokens per second for one stream is memory bandwidth divided by the bytes read per token. A purely hypothetical case shows the effect: if 60 GB of weights were read per token at 400 GB/s, one stream would top out near 6.7 tokens per second. Batching many requests amortizes those reads, which is why a capacity-heavy card can still make sense for serving many agent sessions at once. Those figures are illustrations, not Crescent Island specifications.
What LPDDR5X buys is capacity at lower power and cost. StorageReview reports up to 480 GB per card. TechRadar flags a caveat on that number, covered in the disagreements section below. Neither report gives a process node, software stack or launch date for the card.
Wildcat Lake: the edge chip that lost its base die
Wildcat Lake is the only one of the three you can buy today. TechRadar says it is in mini PCs and laptops under the Core Series 3 name. Per StorageReview, it uses Intel 18A, pairs 2 performance cores with 4 efficiency cores, adds an Xe3 GPU with XMX acceleration, supports LPDDR5X-7467, Wi-Fi 7 and Bluetooth 6.0, and carries an NPU of up to 17 TOPS.
The packaging change is the interesting part. TechRadar says Intel dropped Panther Lake’s Foveros packaging for an organic multi-chip package and removed the base die, shrinking the compute die by 38% and the I/O tile by 15%. A simpler package should cost less to build, which matters for low-priced laptops. The tradeoff shows up in the NPU: 17 TOPS sits below Microsoft’s 40 TOPS Copilot+ requirement, though TechRadar notes that Intel’s own 40 TOPS figure is a platform total across CPU, GPU and NPU.
| Chip | Role | Key specifications | Memory | Status in the reports |
|---|---|---|---|---|
| Diamond Rapids | Data center CPU (Xeon) | Up to 256 cores, 1.28 GB LLC, Intel 18A-P, 128 PCIe Gen6 lanes, CXL 3.0 | 16 channels, up to 12,800 MT/s | 2027 per TechRadar; no Intel date in StorageReview |
| Crescent Island | Inference GPU (Xe3P) | 32 Xe cores, 256 XMX engines, 350 W, air-cooled PCIe | LPDDR5X, up to 480 GB in partner configurations | Launch timing not stated |
| Wildcat Lake | Client and edge SoC (Core Series 3) | 2P + 4E cores, Xe3 GPU, NPU up to 17 TOPS | LPDDR5X-7467 | Shipping in mini PCs and laptops |
Where the reports disagree
Three points differ between sources, and one limit applies to this article as a whole.
- Crescent Island memory. StorageReview gives up to 480 GB. TechRadar says Intel’s press release cites up to 480 GB, but Intel-branded cards are capped at 160 GB, and the larger figure applies only to ODM partner configurations. Which number applies to which product is not settled in these reports. Check Intel’s own materials before planning around either.
- Wildcat Lake packaging. StorageReview calls it Intel’s first UCIe integration in a mainstream client processor. TechRadar describes an organic multi-chip package replacing Foveros. UCIe has a variant for standard organic packages, so both descriptions may be true, but neither outlet says so.
- Diamond Rapids chiplets. The 16-core chiplet detail is TechRadar relaying ServeTheHome, so it is secondhand twice over.
- Source depth. This article rests on press coverage of the talks. I did not review Intel’s slides or newsroom text directly.
What this means for buyers and builders
Server teams planning 2027 refreshes get two concrete planning inputs: PCIe Gen6 lane counts and CXL 3.0 support on the CPU side. Whether a 256-core part with about half the threads of its rival wins on agent workloads depends on software that nobody has benchmarked in public yet.
For inference buyers, the missing number is Crescent Island’s memory bandwidth. Until Intel publishes it, capacity claims say little about throughput. On the client side, Wildcat Lake is a cost-oriented design, and shoppers who need the Copilot+ label should read the NPU line before the platform total.
This section is analysis, not reporting. The specifications above are the part with sources behind them.
Questions readers ask
When does Intel Diamond Rapids ship?
TechRadar reports 2027. StorageReview’s summary of the presentation gives no launch timing, and no Intel date turned up in either source, so treat the year as reported but unconfirmed.
Does Crescent Island use HBM?
No. Both reports say it uses LPDDR5X. That favors capacity and lower power over peak bandwidth, and Intel has not disclosed the bandwidth figure.
What is UCIe?
Universal Chiplet Interconnect Express, an open standard for linking separate dies inside one package. Intel says its three platforms use it alongside Foveros Direct 3D stacking.
Is Wildcat Lake a Copilot+ PC chip?
Per TechRadar, its 17 TOPS NPU is below Microsoft’s 40 TOPS requirement. Intel cites 40 TOPS as a platform total across CPU, GPU and NPU, which is a different measure.
Sources
