The memory supercycle produced two results this month that would have read like typos two years ago. On October 8, Samsung Electronics guided to third-quarter operating profit of about 107.4 trillion won on roughly 195 trillion won in sales. Nine days earlier, on September 30, Micron reported fiscal fourth-quarter revenue of $54.23 billion, GAAP net income of $37.70 billion and a gross margin of 86.8 percent.

Both trace to the same cause. Accelerators built for AI need high-bandwidth memory in quantities that conventional DRAM lines cannot also supply, so supply is tight, and prices and margins have followed it upward.

This post sets out the figures, explains what HBM4 is and why it absorbs so much manufacturing capacity, examines the contracts that shape the next two years, and looks at who is paying for the boom. Samsung’s numbers are guidance, not final results, and several of the Micron segment splits below are an analyst’s estimates. We say which is which. This is reporting, not investment advice.

The Numbers, Side by Side

Samsung Electronics (trillion won)Q3 2026 guidanceQ2 2026Q3 2025
Salesabout 195171.586.06
Operating profitabout 107.4089.4912.17
Operating margin (our arithmetic)about 55%about 52%about 14%

Samsung’s newsroom page labels the figures as estimates and explains that Korean disclosure rules do not allow a range, so the headline numbers are midpoints. TrendForce reports operating profit up about 782 percent from a year earlier, the first time the company has crossed 100 trillion won in a quarter, and says the full earnings release with the divisional breakdown is due October 29.

Micron (fiscal Q4 2026)Reported
Revenue$54.23 billion
GAAP net income$37.70 billion ($32.87 per diluted share)
GAAP gross margin86.8 percent
Fiscal 2026 revenue$133.19 billion
Capital expenditures, net, Q4$10.77 billion
Fiscal Q1 2027 revenue guidance$61.5 billion, plus or minus $1.5 billion

Micron’s figures come from its September 30 filing with the SEC, which does not itself discuss HBM4.

What HBM4 Is, and Why It Eats Wafers

High-bandwidth memory stacks DRAM dies vertically and links them with thousands of tiny vertical channels called through-silicon vias. The stack sits beside the processor on the same package, so data travels millimeters instead of centimeters. Next Platform’s analysis of Micron’s quarter refers to 12-high HBM4 stacks. The newest JEDEC generation also widens the interface to 2,048 bits, double the previous generation, though that detail is general background and not drawn from the quarter’s coverage.

Semiconductor cleanroom with wafers on a robotic carrier

Capacity is where the arithmetic bites. A stack twelve dies tall works only if every die in it is good, and the dies are processed to be stacked, which makes each wafer yield fewer sellable gigabytes than the same wafer made into ordinary DRAM. Next Platform notes that taller stacks at higher speeds raise the chance of defective stacks, expects the problem to worsen with HBM4E and HBM5, and concludes that this drives demand for more DRAM capacity and higher capital spending.

The result spreads outward. A wafer committed to HBM is a wafer not making conventional memory. TrendForce reports that Samsung’s HBM bit shipments rose nearly 50 percent from the prior quarter, while conventional DRAM prices rose sharply and bit shipments stayed roughly flat because supply is tight.

Where Micron’s Revenue Came From

Per the Next Platform breakdown of Micron’s disclosures, DRAM revenue was $39.77 billion, up 4.4 times from a year earlier, and NAND revenue was $14.1 billion, up 6.2 times. Micron’s Cloud Memory business unit, which is dominated by HBM, brought in $16.28 billion at an 83 percent gross margin and a 76 percent operating margin. Prices rose in the high-teens percentage range for DRAM and about 30 percent for flash, while DRAM bit shipments rose only in single digits.

The author also estimates, and Micron does not report, that HBM revenue was about $14.33 billion in the quarter. That would be roughly 36 percent of DRAM revenue and 26 percent of the total, with high-capacity server modules and low-power DRAM at $8.05 billion and all other DRAM at $17.39 billion. Treat those splits as informed guesses.

The Contracts That Shape 2027

Micron’s disclosures, as relayed by Next Platform, describe a different business from the old spot-market memory trade. The company has 26 supplier agreements covering about 35 percent of revenue through fiscal 2030, $32 billion in customer prepayments, and $150 billion in remaining performance obligations, a figure that counts only deals with fixed price floors and committed volumes. Most calendar 2027 HBM supply is contracted at significant year-over-year price increases.

Micron expects memory and flash to be tighter in 2027 and 2028 than in 2026. It sees DRAM bit shipments growing in the mid-20s percent range in 2026 and the low-20s in 2027 and 2028. TrendForce reports that Samsung and Micron both expect tight supply through 2028.

Our reading is that price floors and prepayments make memory look more like a capacity reservation than a commodity. They also push more of the risk onto buyers.

Who Is Paying for It

  • Phones and appliances. TrendForce relays analyst estimates that Samsung’s consumer-device division will lose more than 1 trillion won in the quarter, up from roughly 800 billion in Q2. IDC’s forecast of a record 2026 drop in smartphone shipments, about 16.7 percent as memory costs rise, was cited in an August Semiconductor Engineering roundup.
  • Foundry. Samsung’s chip-contract manufacturing business is expected to stay loss-making, according to the same coverage.
  • Anyone buying conventional DRAM. Prices rose sharply while shipments held flat, so buyers paid more for the same volume.

Competition and Cycle Risk

Micron says it is two generations ahead of China’s CXMT. CXMT announced on September 20 that its fifth-generation platform had entered mass production, claiming an 11.95-nanometer active-area half-pitch and at least 50 percent more dies per wafer than its predecessor. Every figure is the company’s own, and TechNode offers no independent verification. A Semiconductor Engineering roundup from September 25 also reports, citing the Seoul Economic Daily, that Samsung plans to at least double HBM4-family output in 2027. That is a report, not a confirmed plan.

Rows of DRAM memory modules in a warehouse bin

Memory has a long history of booms followed by gluts, as capacity added in good years floods the market later. Micron plans to raise capital spending in fiscal 2027 to expand DRAM output, which is the behavior that has preceded downturns before. The contracts with price floors blunt that risk without removing it. TrendForce lists Chinese competition and possible U.S. chip tariffs among the long-term threats to profitability.

What to Watch

  • October 13 to 15: SEMICON West in San Francisco.
  • October 29: Samsung’s full results with the divisional breakdown, per TrendForce.
  • Micron’s fiscal Q1 2027: the company guided to $61.5 billion in revenue, plus or minus $1.5 billion.
  • HBM yields on taller stacks: the technical risk Next Platform flags for HBM4E and beyond.

Reading the Margins

The ratios are as striking as the totals. Micron’s net income of $37.70 billion on $54.23 billion of revenue is a net margin of about 69.5 percent, a figure Next Platform also calculates, and its operating income of $43.75 billion works out to about 81 percent of revenue. Samsung’s roughly 55 percent operating margin is lower, but it covers an entire conglomerate that includes loss-making phone, appliance and foundry operations alongside a memory business that is clearly earning far more than the average. Next Platform puts Micron’s HBM-heavy cloud memory unit at an 83 percent gross margin and a 76 percent operating margin.

Memory stick over an open PC with an AI accelerator card

Margins like these are the strongest evidence that supply, not demand, is setting the pace. They also explain the capital plans. When a product earns this much, every producer wants more capacity, and the only question is how quickly new fabrication lines can come online.

How Customers Are Responding in Hardware

Buyers are not simply paying the bill. Semiconductor Engineering’s roundups describe several architectural moves aimed at using memory differently. Nvidia has expanded its NVLink Fusion with a variant called NVHBM that puts a custom memory controller inside the HBM stack, and Next Platform says Micron is working with Nvidia on a custom HBM4E implementation of that idea. Qualcomm has described a High Bandwidth Compute design that places a compute die beneath a 3D-stacked low-power DRAM array. And imec modeled a 3D DRAM-on-GPU design that cut peak temperature from 121.7 degrees Celsius to 103.4 degrees Celsius against an HBM-on-GPU baseline, a lab model and not a shipping product.

Each approach tries to get more bandwidth or capacity from a given amount of silicon, or to relieve a thermal limit. None removes the dependence on advanced memory. They do show where engineering effort is heading while supply remains short.

Sources and Verification Notes

Samsung’s figures are guidance midpoints, and operating margins are our own division. One outlet converted Samsung’s profit to dollars without citing an exchange rate, so we omit the conversion. Next Platform’s segment splits are the author’s estimates, and we leave out its comparison of HBM to gold because its inputs are unsourced. The HBM4 interface width is general industry background.