Is Moore’s law dead? Every few years a headline says so, and every few years a chip company answers that it is alive and well. Both camps can be right, because the phrase has never meant one single thing. This piece sorts out what Gordon Moore actually said, which part of the trend has faded, which part continues, and where chip designers are placing their bets now.

What did Moore’s law actually say?

It was an observation, not a law of physics. In 1965 Gordon Moore, then at Fairchild Semiconductor and later a co-founder of Intel, projected that the number of components on a chip at minimum cost would grow by a factor of roughly two each year. He speculated that a chip a quarter of a square inch in size might hold up to 65,000 components by 1975.

In 1975 he revised the pace. The doubling, he said, might happen about every two years by the end of that decade. That is the version people usually quote today, often with a loose gloss that performance doubles every two years or every eighteen months. Moore never framed it quite that way.

The distinction matters, because the claim about transistor counts and the claim about speed have separated. One has slowed gently. The other changed shape a long time ago.

Why did chips stop getting faster by themselves?

For decades, shrinking transistors came with a bonus. Under a rule of thumb called Dennard scaling, smaller transistors used proportionally less power, so a manufacturer could pack in more of them and run them faster without the chip overheating. Then leakage current spoiled the arrangement. Depending on the source, Dennard scaling ended somewhere between 2005 and 2010.

The practical result is familiar to anyone who has noticed that processor clock speeds stopped climbing. The industry responded by adding more cores and specialised circuits instead of pushing a single core faster. Transistor counts kept rising; the free speed boost did not.

So when someone says Moore’s law died in the mid-2000s, they usually mean this. It is a defensible reading, though a different claim from the one Moore made.

Has the doubling slowed down?

Yes, by the testimony of the people running the companies. Moore himself said in 2005 that the trend could not continue forever, because that is the nature of exponentials: push them out far enough and they run into trouble. In 2015, Intel’s then chief executive Brian Krzanich said the company’s cadence had stretched to closer to two and a half years. At the end of 2023, Pat Gelsinger, another Intel chief executive, put it closer to every three years.

Opinions on the label differ sharply. In 2022 Nvidia’s Jensen Huang declared Moore’s law dead, and Gelsinger took the opposite view. Both men sell chips, and both have a commercial reason to frame the matter their way. The source I consulted notes that experts have not agreed on when, or whether, the trend ends.

Raw numbers support a slowdown without a collapse. As of 2025, the GB202 graphics processor has more than 92.2 billion transistors, a figure that would have sounded absurd to the engineers of the 1970s. The issue is how long each doubling takes and how much each one costs.

Why is each step so expensive?

Cost is the quieter story. Extreme ultraviolet lithography, the technique used to print the finest features, requires machines whose price roughly doubles every four years. That is a sort of Moore’s law running in reverse: the tools that make chips follow their own exponential, in cost rather than capability.

The tools arrived in stages: IBM demonstrated 7 nm chips made with EUV in 2015, and Samsung planned 5 nm production combining FinFETs with EUV for 2020. A smaller number of companies can afford the frontier as a result. Moore’s original 1965 statement was about components at minimum cost, so a trend that continues in density but not in cost is, strictly speaking, no longer his law. That is one way engineers frame it. The physics may still permit smaller transistors; the economics decide whether anyone builds them.

What does “3 nanometer” even mean?

Less than it sounds like. Since around 2009, a process node name has been a marketing label for a new generation of manufacturing, not a measurement of any particular feature. It is not tied to gate length, metal pitch, or gate pitch. According to the reference I used, node names stopped tracking gate length around 1994, and the habit of naming by physical size was effectively abandoned by 2009.

One consequence is that a “7 nm” process from one company can resemble a “10 nm” process from another in actual density. Intel’s former 10 nm process had fin tips about 7 nm wide and a density similar to TSMC’s 7 nm. Comparing the labels across manufacturers tells you little; comparing transistor density does better. TSMC’s N5 process, for example, had the highest transistor density in 2019 at 171.3 million per square millimeter.

How are engineers keeping the trend going?

They are changing the transistor, not only shrinking it. Intel demonstrated FinFETs in 2011 at the 22 nm node. In a FinFET the gate wraps the channel on three sides, which curbed the leakage problems that plagued flat transistors. By 2018 the proposed successors were mostly gate-all-around designs, in which the gate surrounds the channel, using nanowires or stacked nanosheets. Samsung and TSMC announced plans for 3 nm gate-all-around nodes for the 2021 to 2022 window, and 2 nm nodes have been listed for 2025; Samsung’s 2024 roadmap included a 2 nm chip in 2025. The concept itself is not new, since Toshiba demonstrated a gate-all-around transistor as far back as 1988. What changed is that manufacturing finally caught up with a drawing-board idea, which is a recurring pattern in this industry: the physics is understood decades before the factory can build it at scale and at a price anyone will pay.

Another route is going upward. Samsung commercialised 3D NAND flash in 2013, starting with 24 layers, and stacked flash has since grown far beyond that. Stacking logic is generally considered harder than stacking memory because of heat, though the idea is old: Toshiba developed a wafer-bonding process for 3D chip packages in 2001 and showed an eight-layer 3D circuit in April 2007.

A third route is to stop treating a processor as one slab of silicon. Chiplets split a design into several small dies placed in one package. Smaller dies can be tested before assembly, which improves yield, and different pieces can be built on different processes. AMD’s Ryzen processors from Zen 2 onward and Intel’s Meteor Lake and Arrow Lake use the approach. Industry standards such as UCIe aim to let chiplets from different makers work together.

What replaces Moore’s law as the guide?

The industry’s own roadmap changed its tune first. The International Technology Roadmap for Semiconductors used Moore’s law to coordinate the whole field from 1998. Its final edition, in 2016, abandoned that focus for an approach called More than Moore, in which the needs of applications such as phones, sensors, and data centres drive what gets built, rather than a fixed cadence of shrinking. The IEEE launched a successor effort, the International Roadmap for Devices and Systems, in 2016.

In practice, gains now come from several directions at once: specialised accelerators for graphics and AI, faster memory, better packaging, and software that wrings more from the hardware. None of these is a doubling every two years. Together they have kept overall computing capability rising, although unevenly across tasks.

New materials are on the horizon, though they remain research. In April 2025, researchers at Fudan University reported a 1 nm-class 32-bit RISC-V chip built with two-dimensional semiconductors. That is a laboratory result and not a production process, and the leap from one to the other has broken many promising ideas before.

Does a bigger transistor count always mean a better device?

No, and flash memory shows why. Counting transistors is easy; deciding what they are for is harder. Samsung’s 1 terabyte flash package from 2019 stacked eight dies of 96-layer memory and amounted to about 2 trillion transistors by one accounting. That is far more than any processor, yet each memory cell does one humble job: it holds a bit.

A processor with a tenth as many transistors may do far more demanding work per switch, because logic has to be fast, hot, and tightly wired. Comparing the two on transistor count alone says little about usefulness. It is worth remembering when a new chip is announced with a record-breaking number.

Where does that leave the answer?

It depends on which claim you test.

  • Component count per chip is still rising, though slower than the two-year rhythm of earlier decades.
  • Cost per transistor is widely argued to have stopped falling reliably at the leading edge, a point that is contested and depends on how costs are counted.
  • Single-thread speed gains largely ended when Dennard scaling did, in the 2005 to 2010 period.
  • Total system performance still improves, driven by architecture and packaging as much as by smaller transistors.

So “dead” is too blunt, and “alive and well” is too comfortable. A fair summary is that the original exponential has bent into something slower and more expensive, while engineers find other places to look for improvement.

Common questions

Who was Gordon Moore?

He was an American chemist and engineer who co-founded Fairchild Semiconductor and later Intel. He published the observation that bears his name in 1965 and refined it in 1975.

Is Moore’s law a law of physics?

No. It is an empirical trend that became an industry target. Companies planned around it, which helped it hold for as long as it did.

Will transistors stop shrinking?

At some point, atomic dimensions set a limit, and Moore himself said the trend could not go on forever. Where that limit lies in practice depends on cost as much as physics, and experts disagree on the date.

Are chips with smaller “nanometer” numbers always better?

Not necessarily. Node names are marketing labels since about 2009, so density, power use, and performance have to be compared directly.

Does a slowdown mean computers stop improving?

No. Gains continue through specialised hardware, chiplets, 3D stacking, and software. They arrive less predictably than the old shrink-and-speed-up cycle.

What to remember

Moore’s law began as a 1965 projection about components per chip, was adjusted to a two-year doubling in 1975, and was never a guarantee. Speed gains by shrinking ended around 2005 to 2010, and the doubling has slowed to something like two and a half to three years by the account of Intel’s own leaders. What continues is a mix of new transistor shapes, stacked layers, chiplets, and specialised designs. Whether you call that Moore’s law depends on how generous your definition is.

Further reading

A widely read popular history of the semiconductor industry. See it on Amazon (affiliate link)

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Sources